Protocol Decoder Logic Analyzer
Real-time serial bus protocol simulator and physical layer fault injector for UART, I2C, and SPI. Inspect square-wave voltage transitions, calibrate receiver clock drift, inject EMI line glitches, and inspect decoded protocol packets on the fly.
Raw Physical Voltage Transitions & Logic Analyzer Trace
Decoded Protocol Stream & Packet Inspector
| # | Timestamp (µs) | Raw Bits Sampled | Decoded Hex | ASCII Char | Parity Check | Stop Bit Check | Frame Status | Diagnostic Details |
|---|---|---|---|---|---|---|---|---|
| 0 | 17.4 µs | 01010011 | 0x53 | S | Sampled: 0 (Exp: 0) | HIGH (1) | OK | Byte #0 verified clean |
| 1 | 125.9 µs | 01011001 | 0x59 | Y | Sampled: 0 (Exp: 0) | HIGH (1) | OK | Byte #1 verified clean |
| 2 | 234.4 µs | 01001110 | 0x4E | N | Sampled: 0 (Exp: 0) | HIGH (1) | OK | Byte #2 verified clean |
UART Asynchronous Serialization
Asynchronous serial lacks a distributed clock line. Receiver oscillators synchronize on the falling edge of the Start bit and sample bits at (1.5 + i) * T_rx. Because timing errors accumulate linearly over 10 bit periods, an oscillator discrepancy exceeding ~4.5% causes the Stop bit sample to drift into the transition edge, raising a hardware Framing Error.
I2C Wired-AND Bus Physics
I2C devices cannot actively drive lines HIGH. Bus lines (SDA and SCL) are pulled to 3.3V via 4.7kΩ resistors, and transceivers only pull lines to Ground (LOW). This prevents bus shorts during multi-master arbitration and enables clock stretching, where slow peripheral slaves hold SCL LOW to throttle the master.
SPI Synchronous Shift Registers
SPI distributes a dedicated clock (SCK), eliminating baud rate oscillator drift entirely. However, the receiver shift register must strictly match the peripheral's Clock Polarity (CPOL) and Clock Phase (CPHA). Mismatching CPHA causes data to be sampled during signal transition slew rather than the steady state, shifting all incoming bytes by 1 bit.